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| July 2005 rev 0.2 3.3V 1:8 LVCMOS PLL Clock Generator Features 1:8 PLL based low-voltage clock generator Supports zero-delay operation 3.3V power supply Generates clock signals up to 125MHz PLL guaranteed to lock down to 145MHz, output frequency = 36.25MHz Maximum output skew of 150 pS Differential LVPECL reference clock input External PLL feedback Drives up to 16 clock lines 32 lead LQFP & TQFP Packages Ambient temperature range 0C to +70C Pin and function compatible to the ASM5I9653A running at either 4x or 8x of the reference clock frequency. The ASM5I9653A is guaranteed to lock in a low power PLL mode in the high frequency range (VCO_SEL = 0) down to PLL = 145 MHz or Fref = 36.25MHz. The ASM5I9653A has a differential LVPECL reference input long with an external feedback input. The device is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The ASM5I9653A is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the ASM5I9653A outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm2 32-lead LQFP & TQFP Packages. MPC953,MPC9653A and MPC9653 Functional Description The ASM5I9653A utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the ASM5I9653A requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 25 to 62.5MHz or 50 to 125MHz. The two available post-PLL dividers selected by VCO_SEL (divide-by-4 or divide-by-8) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the ASM5I9653A is Alliance Semiconductor 2575, Augustine Drive * Santa Clara, CA * Tel: 408.855.4900 * Fax: 408.855.4999 * www.alsc.com Notice: The information in this document is subject to change without notice. July 2005 rev 0.2 Block Diagram ASM5I9653A Figure 1. ASM5I9653A Logic Diagram Pin Configuration ASM5I9653A Figure 2. ASM5I9653A 32-Lead Package Pinout (Top View) 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 2 of 13 July 2005 rev 0.2 Table 1: Pin Configuration Pin # 8,9 2 32 31 30 10 26,24,22,20,18,16,14,12 28 7,13,17,21,25,29 1 ASM5I9653A Pin Name PCLK, PCLK FB_IN VCO_SEL BYPASS PLL_EN MR/OE Q0-7 QFB GND VCC_PLL I/O Input Input Input Input Input Input Output Output Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Function PECL reference clock signal PLL feedback signal input, connect to QFB Operating frequency range select PLL and output divider bypass select PLL enable/disable Output enable/disable (high-impedance tristate) and device reset Clock outputs Clock output for PLL feedback, connect to FB_IN Negative power supply (GND) PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation No Connect 11,15,19,23,27 3,4,5,6 VCC NC Supply - VCC - Table 2: FUNCTION TABLE Control PLL_EN Default 1 0 Test mode with PLL bypassed. The reference clock (PCLK) is substituted for the internal VCO output. ASM5I9653A is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Test mode with PLL and output dividers bypassed. The reference clock (PCLK) is directly routed to the outputs. ASM5I9653A is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. VCO / 1 (High frequency range). fREF =fQ0-7 =4 . fVCO 1 Selects the VCO output1 BYPASS 1 Selects the output dividers. VCO_SEL 1 VCO / 2 (Low output range). fREF =fQ0-7 =8 . fVCO Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (PCLK). MR/OE 0 Outputs enabled (active) Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1. 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 3 of 13 July 2005 rev 0.2 Table 3: GENERAL SPECIFICATIONS Symbol VTT MM HBM LU CPD CIN ASM5I9653A Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance Min 200 2000 200 Typ VCC/2 Max Unit V V V mA Condition 10 4.0 pF pF Per output Inputs Table 4: ABSOLUTE MAXIMUM RATINGS1 Symbol VCC VIN VOUT IIN IOUT TS Characteristics Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage Temperature Min -0.3 -0.3 -0.3 Max 3.9 VCC+0.3 VCC+0.3 20 50 Unit V V V mA mA C Condition -65 125 Table 5: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0C to 70C) Symbol VIH VIL VPP VCMR VOH VOL ZOUT IIN ICC_PLL ICCQ5 2 Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output impedance Input Current 4 Min 2.0 (PCLK) (PCLK) 300 1.0 2.4 Typ Max VCC +0.3 0.8 VCC-0.6 0.55 0.30 Unit V V mV V V VV A mA mA Condition LVCMOS LVCMOS LVPECL LVPECL IOH=-24 mA3 IOL=24mA IOL=12mA VIN=VCC or GND VCC_PLL Pin All VCC Pins 14 -17 200 10 15 15 Maximum PLL Supply Current Maximum Quiescent Supply Current Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 2 VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 3 The ASM3P9653A is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. The ASM3P9653A meets the VOH and VOL specification of the ASM3P953 (VOH > VCC-0.6V at IOH=-20mA and VOL > 0.6V at IOL=20mA). 4 Inputs have pull-down or pull-up resistors affecting the input current. 5 OE/MR=1 (outputs in high-impedance state). 1 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 4 of 13 July 2005 rev 0.2 ASM5I9653A Table 6: AC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0C to 70C)6 Symbol fREF fVCO fVCOlock fMAX VPP VCMR t(O) tPD tsk(O) tsk(PP) DC tR,tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT(O) BW tLOCK 13 Characteristics Input reference frequency PLL mode, external feedback /4 feedback7 8 /8 feedback 9 Min 50 25 0 200 145 50 25 450 1.2 2 -75 1.2 3.0 Typ Max 125 62.5 200 500 500 125 62.5 1000 VCC-0.75 125 3.3 7.0 150 1.5 55 1.0 7.0 6.0 100 100 25 Unit MHz MHz MHz MHz MHz MHz MHz mV V nS pS nS nS pS nS % nS nS nS pS pS pS MHz Condition PLL locked PLL locked Input reference frequency in PLL bypass mode VCO operating frequency range10,11 VCO lock frequency range Output Frequency Peak-to-peak input voltage Common Mode Range Input Reference Pulse Width14 12 8 /4 feedback /8 feedback9 PCLK PCLK PLL locked PLL locked LVPECL LEPVCL PLL locked tPW,MIN Propagation Delay (static phase offset)15 PCLK to FB_IN Propagation Delay PLL and divider bypass (BYPASS=0), PCLK to Q0-7 PLL disable (BYPASS=1 and PLL_EN=0), PCLK to Q0-7 Output-to-output Skew16 Device-to-device Skew in PLL and divider bypass17 Output duty cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-cycle jitter Period Jitter 18 I/O Phase Jitter RMS (1 ) PLL closed loop bandwidth19 PLL mode, external feedback Maximum PLL Lock Time BYPASS=0 PLL locked 0.55 to 2.4V 45 0.1 50 / 4 feedback /8 feedback9 8 0.8-4 0.5 -1.3 10 mS 6 7 AC characteristics apply for parallel output termination of 50 to VTT. /4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0. 8 /8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0. 9 In bypass mode, the ASM3P9653A divides the input reference clock. 10 The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO / FB. 11 fVCO is frequency range where AC parameters are guaranteed. 12 fVCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO. 13 VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR 14 range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(O ). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF . 100% and DCREF,MAX = 100% - DCREF,MIN. E.g. at fREF=100 MHz the input duty cycle range is 20% < DC < 80%. 15 16 Valid for fREF=50 MHz and FB=/8 (VCO_SEL=1). For other reference frequencies: t(O ) [ps] = 50 ps (1/(120 . fREF)). See application section for part-to-part skew calculation in PLL zero-delay mode. 17 For a specified temperature and voltage, includes output skew. 18 I/O phase jitter is reference frequency dependent. See application section for details. 19 -3 dB point of PLL transfer characteristics. 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 5 of 13 July 2005 rev 0.2 APPLICATIONS INFORMATION Driving Transmission Lines The ASM5I9653A supports output clock frequencies from 25 to 125MHz. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500MHz for BYPASS PLL_ EN VCO_ SEL 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 Operation Test mode: PLL and divider bypass Test mode: PLL bypass Test mode: PLL bypass PLL mode (high frequency range) PLL mode (low frequency range) ASM5I9653A stable and optimal operation. Two operating frequency ranges are supported : 25 to 62.5MHz and 50 to 125MHz. Table 9 illustrates the configurations supported by the ASM5I9653A. PLL zero-delay is supported if BYPASS=1, PLL_EN=1 and the input frequency is within the specified PLL reference frequency range. Frequency Ratio fQ0-7 =fREF fQ0-7 =fREF / 4 fQ0-7 =fREF / 8 fQ0-7 =fREF fQ0-7 =fREF Output range (fQ0-7) 0-200MHz 0-50MHz 0-25MHz 50 to 125MHz 25 to 62.5MHz VCO n/a n/a n/a fVCO =fREF 4 fVCO =fREF 8 Power Supply Filtering The ASM5I9653A is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA_PLL power supply impacts the device characteristics, for instance I/O jitter. The ASM5I9653A provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the ASM5I9653A. Figure 3 illustrates a typical power supply filter scheme. The ASM5I9653A frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCC_PLL pin) is typically 10 mA (15 mA maximum), assuming that a minimum of 2.985V must be maintained on the VCC_PLL pin. should provide attenuation greater than 40 dB for noise whose spectral content is above 100kHz. In the example RC filter shown in Figure 3. "VCC_PLL Power Supply Filter", the filter cut-off frequency is around 4 kHz and the noise attenuation at 100kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the ASM5I9653A has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the ASM5I9653A in zero-delay applications Nested clock trees are typical applications for the ASM5I9653A. Designs using the ASM5I9653A as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the ASM5I9653A clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase long-term jitter), feedback path delay and the output-tooutput skew error relative to the feedback output. ASM5I9653A Figure 3. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 6 of 13 July 2005 rev 0.2 Calculation of part-to-part skew The ASM5I9653A zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more ASM5I9653A are connected together, the maximum overall timing uncertainty from the common PCLK input to any output is: tSK(PP) = t(O) + tSK(O) + tPD, LINE(FB) + tJIT(O) CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: ASM5I9653A resulting in a worst case timing uncertainty from input to any output of -197 pS to 297 pS (at 125MHz reference frequency) relative to PCLK: tSK(PP) = [-17pS...117pS] + [-150pS...150pS] + [(10pS . -3)...(10pS . 3)] + tPD, LINE(FB) tSK(PP) = [-197pS...297pS] + tPD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 5. .Max. I/O Jitter versus frequency. can be used for a more precise timing performance analysis. Figure 5. Maximum I/O Jitter vs Frequency Driving Transmission Lines The ASM5I9653A clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the ASM5I9653A clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6 "Single versus Dual Transmission Lines" Illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the ASM5I9653A clock driver is effectively doubled due to its capability to drive multiple lines. Figure 4. ASM5I9653A max device-to-device skew Due to the statistical nature of I/O jitter a RMS value (1 ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 10. Table 10: Confidence Factor CF CF 1 2 3 4 5 6 Probability of clock edge within the distribution 0.68268948 0.95449988 0.99730007 0.99993663 0.99999943 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% ( 3) is assumed, 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 7 of 13 July 2005 rev 0.2 ASM5I9653A OUTPUT BUFFER IN 14 RS=36 Z0=15 OUTA ASM5I9653A ASM5I9653A OUTPUT BUFFER IN 14 RS=36 Z0=15 OUTB0 RS=36 Z0=15 OUTB1 Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 .Single versus Dual Line Termination Waveforms show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the ASM5I9653A output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the ASM5I9653A. The output waveform in Figure 7 Single versus Dual Line Termination Waveforms shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 / (RS+R0 +Z0)) Z0 = 50 || 50 RS = 36 || 36 R0 = 14 VL = 3.0 ( 25 (18+14+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 8 .Optimized Dual Line Termination should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. ASM5I9653A OUTPUT BUFFER IN 14 RS=22 RS=22 Z0=15 Z0=15 14 + 22 _ 22 = 50 _ 50 25 = 25 Figure 8. Optimized Dual Line Termination 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 8 of 13 July 2005 rev 0.2 ASM519653A ASM5I9653A Figure 9. PCLK ASM5I9653A AC test reference Figure 16. Output Transition Time Test Reference 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 9 of 13 July 2005 rev 0.2 Package Diagram 32-lead TQFP Package ASM5I9653A SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 a e Inches Min Max .... 0.0020 0.0374 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0472 0.0059 0.0413 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7 Millimeters Min Max ... 0.05 0.95 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 0.8 BASE 1.2 0.15 1.05 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.2 7 0.03937 REF 1.00 REF 0.031 BASE 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 10 of 13 July 2005 rev 0.2 ASM5I9653A 32-lead LQFP Package SECTION A-A Dimensions Symbol A A1 A2 D D1 E E1 L L1 T T1 b b1 R0 e a Inches Min Max .... 0.0020 0.0531 0.3465 0.2717 0.3465 0.2717 0.0177 0.0035 0.0038 0.0118 0.0118 0.0031 0 0.0630 0.0059 0.0571 0.3622 0.2795 0.3622 0.2795 0.0295 0.0079 0.0062 0.0177 0.0157 0.0079 7 Millimeters Min Max ... 0.05 1.35 8.8 6.9 8.8 6.9 0.45 0.09 0.097 0.30 0.30 0.08 0 1.6 0.15 1.45 9.2 7.1 9.2 7.1 0.75 0.2 0.157 0.45 0.40 0.20 7 0.03937 REF 1.00 REF 0.031 BASE 0.8 BASE 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 11 of 13 July 2005 rev 0.2 Ordering Information Part Number ASM5I9653A-32-ER ASM5I9653A-32-LR ASM5I9653AG-32-ER ASM5I9653AG-32-LR ASM5I9653A Marking ASM5I9653A ASM5I9653A ASM5I9653AG ASM5I9653AG Package Type 32-pin TQFP 32-pin LQFP -Tape and Reel 32-pin TQFP, Green 32-pin LQFP -Tape and Reel, Green Operating Range Industrial Industrial Industrial Industrial Device Ordering Information ASM 5I9653A F-32-LR R = Tape & reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 12 of 13 July 2005 rev 0.2 ASM5I9653A Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Part Number: ASM5I9653A Document Version: 0.2 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 3.3V 1:8 LVCMOS PLL Clock Generator Notice: The information in this document is subject to change without notice. 13 of 13 |
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